This invention generally relates to phase-locked loop frequency synthesizers, and more specifically, to measuring parameters of phase-locked loop frequency synthesizers.
Phase-locked loop frequency synthesizers, generally referred to as phase-locked loops or PLLs, are devices that generates an output signal with a frequency that is a function of a reference input signal. PLLs are used in many systems such as data processing systems, communication systems, and audio and video processing systems. When a PLL is implemented in a system, the frequency of the output signal of the PLL may change many times. For example, the frequency of this output signal may change at the start-up of the system, or when the system changes from one channel to another.
The PLL may include certain components connected in a feedback loop. For example, the components in a PLL may include a phase frequency detector (PFD), a charge pump (CP), a loop filter, and a voltage controlled oscillator (VCO). The PLL may additionally include a feedback frequency divider in applications where the VCO frequency is designed to be a multiple of the reference frequency.
In one example, the PFD can compare a reference signal provided by a suitable signal generator such as an oscillator to an output signal provided as feedback from the VCO. Based on these signals, the PFD can determine differences between the signals and express these differences as up or down pulses to the charge pump. The charge pump can then provide charge to the loop filter, which filters the charge pump output to the tuning port of the VCO. Upon receiving a signal from the charge pump via the loop filter, the VCO can generate an output signal having a frequency based on the voltage level of the input signal provided by the loop filter. Signals generated by the VCO can be fed back to the PFD to complete the feedback loop between the PFD, the charge pump, the loop filter and the VCO.
The absolute values of the operating parameters of the components that are part of a PLL often depend upon temperature and supply voltage. Furthermore, these values can also vary due to manufacturing tolerances. For instance, the time constants and settling behavior of a PLL are dependent on physical elements such as resistors and capacitors that may have a significant variation over process, temperature and supply voltage. In addition, in variable output frequency synthesizers, the natural frequency, loop bandwidth, and damping factor of the PLL are dependent on the feedback divider modulus as well as the frequency of operation.
Dynamic analysis of a control system is usually performed using the transfer function, which is a mathematical representation of the relationship between the input signal and the output signal of the system. The open loop phase domain transfer function of a PLL typically contains two integrators and a stabilizing zero. One of the integrators is a result of the phase relationship between the VCO input and output. The other integrator and the zero are contained in the loop filter.
The relationship between the phase of the input signal to the output signal of a type II PLL can be characterized with parameters: wn, ζ and N.
                                          θ            out                                θ                          i              ⁢                                                          ⁢              n                                      =                              1            N                    ⁢                                                    2                ⁢                                                                  ⁢                ζ                ⁢                                                                  ⁢                                  ω                  n                                ⁢                s                            +                              ω                n                2                                                                    s                2                            +                              2                ⁢                                                                  ⁢                ζ                ⁢                                                                  ⁢                                  ω                  n                                ⁢                s                            +                              ω                n                2                                                                        (        1        )            Where N is the division ration, where ωn=√{square root over (KdK0K2)} and
  ζ  =                    K        1            2        ⁢                                                      K              d                        ⁢                          K              0                                            K            2                              .      Where:K1=Gain through the proportional path.K2=Gain of the integral path.Kd=Phase detector gainK0=The VCO gain
In many systems, it is desirable to fix the location of the PLL's zeros and poles, in order to have a well known relationship between the phases of the input and output signals, and to control the PLL close to carrier phase noise. In a practical PLL, the locations of the poles and zeros are functions of the gains of the small signal components within the loop (K1, K2 and K0). The gains of these components can vary significantly across process and operating conditions. For example, the VCO's voltage to frequency transfer function is nonlinear such that the small signal gain of the VCO at two frequencies within a few percent of each other can have a ratio of 3:1 or greater. Other loop parameters, such as the Charge pump gain and loop filter impedances, are also susceptible to random variation. The net result is that the dynamics of an un-calibrated PLL exhibit large amounts of variation.
There are two parts to calibration of the PLL dynamics; measuring the locations of the poles and zeros, and adjusting the positions of the poles and zeros. Adjusting the positions of the poles and zeros in a locked PLL is achieved by adjusting the size of the loop capacitor, resistor, and charge pump currents. The more challenging task is the measurement of the positions of the poles and zeros in the presences of offsets and nonlinearities, which are typically present in a PLL.
The prior art includes techniques for measuring a PLL's bandwidth by adding phase steps to the PLL, and measuring the time until the phase of the PLL crosses zero. The phase steps are added to the loop by changing the dividers count value by one, for one reference cycle. In the prior art, a digital “bang-bang” phase detector is placed in parallel with the PLL's phase detector. This digital phase detector detects which of the rising edges of the two input clocks arrives first. By measuring the time it takes for the output of the digital phase detector to change polarity, the time at which the phase of the PLL has crossed zero is measured.
There are several important practical details which will limit the effectiveness of prior art techniques. A practical PLL can have a phase offset at its input due to circuit non-idealities (charge pump current miss-match, capacitor leakage, etc). A crossover detection circuit (e.g. a bang-bang phase detector) will have additional offsets which are distinct from the PLL's offsets. A small offset can lead to a very large error in the time-to-crossover measurement, limiting the effectiveness of prior art.
The errors caused by offsets will be less significant if the magnitude of the phase step is increased. However, if the phase step is large, then the PLL non-linearities can also cause significant errors (e.g. the VCO control voltage moves to a different point on its non-linear tuning curve, or the proportional path saturates).